AMS Layout Engineer

Job description

Job Description – AMS Layout Engineer (SMOS10HV Technology) Job Title AMS Layout Engineer – SMOS10HV Experience 3–8 Years (can be adjusted based on hiring needs) Location Kolkata/Bangalore/Hyderabad Job Summary We are seeking a skilled AMS (Analog Mixed-Signal) Layout Engineer with hands-on experience in SMOS10HV technology. The candidate will be responsible for implementing high-quality analog and mixed-signal layouts from schematics, ensuring compliance with design specifications, foundry rules, and signoff requirements. The ideal candidate should possess strong expertise in floorplanning, layout execution, DRC/LVS closure, parasitic extraction, and post-layout support while collaborating closely with circuit design engineers throughout the development cycle. Key Responsibilities • Develop transistor-level and block-level Analog Mixed-Signal (AMS) layouts in SMOS10HV technology. • Create and optimize floorplans considering performance, matching, area, routing, and reliability requirements. • Translate sub-block schematics into physical layouts while maintaining the same hierarchy used in simulations. • Implement layouts according to design documentation, layout guidelines, customer feedback, review comments, and back-annotation requirements. • Ensure one-to-one correspondence between layout implementation and parameterized devices used in schematic simulations. • Perform Design Rule Check (DRC) and resolve violations until achieving a clean signoff database. • Perform Layout Versus Schematic (LVS) verification and resolve discrepancies until successful closure. • Ensure compliance with all foundry-specific layout rules and process requirements. • Generate extracted netlists and provide them to Design Engineers for post-layout simulation and back-annotation activities. • Participate in layout reviews and implement corrective actions based on review findings. • Maintain and update block review documentation with layout implementation details, observations, and recommendations. • Work closely with circuit designers to optimize layout quality, performance, and manufacturability. • Support tape-out activities and ensure timely delivery of layout milestones. Required Qualifications • Bachelor's or Master's degree in Electronics Engineering, VLSI, Microelectronics, or a related field. • Hands-on experience in SMOS10HV process technology. • Strong experience in Analog Mixed-Signal (AMS) Layout Design. • Good understanding of: o Analog layout methodologies o Device matching techniques o Symmetry requirements o Common-centroid layouts cyient.com 2 o Interdigitated structures o Guard rings and shielding • Experience performing: o DRC o LVS o Parasitic Extraction (PEX) o Layout signoff activities • Ability to interpret schematics and convert them into optimized physical layouts. • Strong understanding of hierarchy-based layout implementation. Preferred Skills • Experience in: o High-voltage analog layouts o Power Management ICs (PMIC) o Automotive semiconductor products o Mixed-signal IP development • Knowledge of ESD and latch-up protection concepts. • Understanding of post-layout simulation methodologies. • Familiarity with reliability and manufacturability requirements. EDA Tools Experience with one or more of the following: • Cadence Virtuoso • Mentor Calibre (DRC/LVS/PEX) • Cadence Pegasus • Synopsys IC Validator • Custom Compiler Key Competencies • Strong debugging and problem-solving skills. • Attention to detail and layout quality. • Effective communication and collaboration with design teams. • Ability to work independently and manage complete layout ownership. • Strong documentation and review skills. Keywords AMS Layout, Analog Layout, Mixed-Signal Layout, SMOS10HV, High Voltage Layout, Floorplanning, DRC, LVS, PEX, Layout Signoff, Cadence Virtuoso, Calibre, PMIC, Automotive Semiconductor.