DFT Lead Engineer – Digital & Mixed-Signal Semiconductor Design

Job description

You know the difference between a chip that *passes* test and one that *shouldn't have* . At **Texas Instruments** , our DFT team is the last line of defense — and the first line of quality. We're looking for a DFT Lead who doesn't just implement test strategies — they **define them, own them, and raise the bar on them** . **📌 About the Role** Texas Instruments is seeking a **DFT Lead** to join our semiconductor design organization — one of the most technically rigorous and impactful teams in the global chip industry. As the **DFT Lead** , you'll play a pivotal role in shaping how TI designs for testability across the full product development lifecycle. From defining DFT specifications and driving ATPG strategies to leading silicon bring-up and post-silicon debug, your fingerprint will be on every product that ships. You'll lead and mentor a team of DFT engineers, collaborate cross-functionally with Design, Verification, and Manufacturing teams, and continuously evolve TI's DFT methodologies, tools, and processes. This is a role that demands both **deep technical expertise and genuine leadership instinct** . If you're the kind of engineer who sees a complex design and immediately thinks about scan architecture, fault coverage, and yield impact — this role was built for you. **🛠️ Key Responsibilities** - Develop and execute **DFT methodologies, strategies, and guidelines** to maximize test coverage, minimize test cost, and optimize production yield - Define and review **DFT specifications** — including scan insertion, test compression, boundary scan, memory BIST, and ATPG patterns — ensuring compliance with IEEE and industry standards - Evaluate and select **appropriate DFT methodologies** based on design complexity, coverage requirements, and time-to-market constraints - Work closely with the **design team** to influence design decisions early, ensuring DFT requirements are met without compromising performance, power, or area - Collaborate with **cross-functional teams** — Design, Verification, and Manufacturing — to define and drive DFT implementation throughout the product lifecycle - Drive **continuous improvement** in DFT methodologies, tools, and processes to enhance efficiency, quality, and reliability - Perform **DFT sign-off activities** — including coverage analysis, ATPG fault coverage analysis, DFT-related timing analysis, first-pass silicon bring-up, and post-silicon debug - Stay current with **emerging DFT techniques, industry trends, and semiconductor testing advancements** — and translate that knowledge into practice **✅ Required Skills** - **Bachelor's or Master's degree** in Electrical Engineering, Computer Engineering, or related field - **Minimum 5 years** of DFT experience with a focus on digital and mixed-signal designs in the semiconductor industry - Strong proficiency in **DFT EDA tools** — Cadence Modus, Genus, and related toolchains - Hands-on experience with **ATPG, scan insertion, and test pattern generation** for high-complexity designs - Expertise in **DFT methodologies** — scan compression, boundary scan, memory BIST, and JTAG (IEEE 1149.1) - Familiarity with **silicon bring-up and post-silicon debug** workflows - Strong knowledge of **DFT industry standards and best practices** - Experience with **scripting languages** (Perl, Python, TCL) for automation and data analysis - Strong **analytical and problem-solving skills** — able to identify, root-cause, and resolve DFT challenges across complex design environments **🌟 Preferred Qualifications** - Proven experience leading **DFT sign-off** for high-complexity SoC or mixed-signal IC designs - Hands-on experience with **logic BIST (LBIST)** and **embedded deterministic test (EDT)** - Background in **DFT for mixed-signal and analog IP** blocks - Experience with **production test correlation** and yield analysis - Familiarity with **DFT-aware physical design** — scan routing, clock domain partitioning, test mode timing - Track record of **leading and mentoring** junior-to-mid DFT engineers on multi-project programs - Exposure to **IEEE 1500, 1687 (iJTAG)** or other advanced DFT standards - Experience with **Tessent, Synopsys DFT Compiler** , or multi-vendor DFT tool flows **🚀 Why Join Texas Instruments?** **🔬 Work on Designs That Matter** TI's semiconductor portfolio spans industrial, automotive, personal electronics, and communications. As DFT Lead, your work directly impacts the quality, reliability, and yield of products shipped to millions of end users globally. **🧠 Technical Leadership With Real Authority** This isn't a DFT execution role — you'll define strategy, lead methodology, and own sign-off. Your decisions shape product outcomes from design through production. **📈 Career Growth on Your Terms** TI offers structured career tracks across both **technical (Senior→ Lead → Fellow)** and **people leadership** paths, with genuine investment in your development. **🤝 Cross-Functional Collaboration at Scale** You'll work with design, verification, manufacturing, and test engineering teams — building a network and impact that spans the full semiconductor development ecosystem. **💰 Competitive Compensation & Stability** Market-leading salary, long-term incentives, comprehensive benefits, and the financial strength of a global Fortune 500 semiconductor leader. **🌱 A Culture of Continuous Improvement** TI actively invests in evolving its methodologies, tools, and processes — and DFT is a critical pillar of that investment. You'll have the resources and mandate to drive real change. **📣 Call to Action** The best DFT engineers don't wait for test problems to surface — they design them out from the start. If that mindset defines how you work, A **pply Now** .