Director - Senior Principal Engineer

Job description

Physical Design Lead - CyientSemi Job Summary: CyientSemi is seeking an experienced and highly motivated Physical Design Lead to guide and mentor a team in the execution of complex ASIC physical design projects. This role involves overseeing the full physical design flow from netlist to GDSII, ensuring timely delivery of high-quality, high-performance, and power-efficient designs. Job Responsibilities: \\* Lead and manage a team of physical design engineers, providing technical guidance, mentorship, and performance feedback. \\* Drive the full physical design flow for complex SoC/ASIC projects, including floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure (STA), signal integrity (SI) analysis, power integrity (PI) analysis, formal verification, and physical verification (DRC/LVS). \\* Develop and implement strategies for achieving aggressive power, performance, and area (PPA) targets. \\* Collaborate closely with front-end design, DFT, and architecture teams to ensure seamless integration and design closure. \\* Define and implement methodologies, scripts, and automation flows to improve efficiency and design quality. \\* Conduct critical design reviews and provide technical leadership in problem-solving and issue resolution. \\* Contribute to the development of project schedules, resource planning, and risk mitigation strategies. \\* Stay abreast of industry trends, new technologies, and best practices in physical design. \\* Document design methodologies, results, and provide clear communication to stakeholders. Job Qualifications: \\* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field. \\* 15+ years of industry experience in ASIC/SoC physical design, with at least 3 years in a lead or supervisory role. \\* Proven expertise in all aspects of physical design, including floorplanning, P&R, CTS, STA, DRC/LVS. \\* Strong command of industry-standard EDA tools (e.g., Synopsys Fusion Compiler/Innovus, Cadence Genus/Tempus/Voltus/Joules, Ansys RedHawk/PathFinder). \\* In-depth knowledge of advanced technology nodes (e.g., 7nm, 5nm, 3nm). \\* Hands-on experience with scripting languages (e.g., Tcl, Perl, Python) for automation and flow development. \\* Solid understanding of timing constraints, power optimization techniques, and signal integrity challenges. \\* Excellent leadership, communication, and interpersonal skills. \\* Ability to mentor junior engineers and foster a collaborative team environment. \\* Strong problem-solving abilities and a proactive approach to issue resolution.