IC Design Engineer

Job description

**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of PR flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO PR, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for PR, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone .