Infra Design Verification Engineer

Job description

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering **General Summary:** As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. **Minimum Qualifications:** Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Additional Job Description We are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team - Create DV infrastructure for verification - Integrate VIPs - Create and execute test plans, debug failures, write assertions, close code and functional coverage - Ensure high quality verification - Working with all stakeholders to ensure program success **Minimum Qualifications** Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field. 5+ years Hardware Engineering experience or related work experience. **Preferred Qualifications** Following skill set is required: - Strong Debug, UVM, System Verilog - Understanding Specs and Standards and developing relevant test plans - Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved - Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening - Thorough understanding of Digital design concepts - Thorough understanding dv methodologies and tools - Good understanding of LPDDR4/LPDDR5 protocols - Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite