IO and Mixed Signal Layout Design Engineer

Job description

Job Description: • Design full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies. • Drive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric. • Perform comprehensive layout verification to ensure high quality and compliance • Complete ownership from end to end deliverables with quality within the schedule. • Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites. **Skills and Qualifications Required:** • B.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experience • Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification • Solid understanding of Planar and FinFET layouts and process technology • Good understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements • In-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts • Proficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools. • Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc • Familiar with the Physical Design flow: LEF generation and PnR • Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus. • Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sites • Able to lead, train junior engineers, and manage projects effectively. • Self-motivated, capable of working independently, and a strong collaborative team player. R027038