Ip Physicial Design Engineer (Sr. Lead/Staff)

Job description

Job Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Responsibilities • 6 to 10 years of relevant experience in Physical Design • Extensive hands-on experience in the Physical Design flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. • Strong expertise in timing closure using PrimeTime and/or Tempus, with a thorough understanding of setup/hold analysis, OCV/POCV methodologies, clocking architectures, and STA signoff. • Proven experience working on advanced technology nodes and delivering IP-level Physical Design solutions, including end-to-end ownership from netlist to GDS. • Demonstrated ability to analyze, debug, and resolve timing, congestion, DRC/LVS, EM/IR, and integration-related challenges. • Familiarity with Mixed-Signal and High-Speed IPs, with the ability to collaborate effectively across Front-End, CAD, STA, and signoff teams. • Excellent analytical and problem-solving skills, with strong attention to detail and the ability to manage multiple programs within demanding project schedules. • Strong automation and scripting capabilities; familiarity with AI-driven methodologies and applications in design flows is considered an advantage. • Proficiency in Tcl and Python scripting for flow automation, data analysis, and design debug, driving improved efficiency and productivity. • Hands-on experience with industry-leading EDA tools for Physical Design and signoff, including place-and-route, STA, and physical verification tools. • Effective communication and stakeholder management skills, coupled with a collaborative, team-oriented approach to driving cross-functional execution and closure.