Lead Design Engineer

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities : • Design Verification for interconnect IP and Tensilica Processor subsystems. • Relevant experience in interconnect and subsystems is strongly preferred • Crafting verification plans and executing on those plans to verify highly complex and configurable designs. • Responsible for coverage collection and closure • Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope • Responsible for creating / working with UVM based DV environment. Required Skills and Experience: • 7+ years of design verification experience • BS (or higher) in EE/Computer Engineering • Strong technical and interpersonal skills • Excellent knowledge of Interconnects, NoCs and design verification fundamentals. • Excellent knowledge and command over AMBA protocols like AXI, AHB and APB. • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches • Exposure to scripting languages like Perl, Unix shell or similar languages • Understanding of Coherency concepts will be a plus • Experience with Formal Verification will be a plus • Experience with development of fully automated flows • Experience with Gate Level Simulations • Excellent written and oral communication skills necessary • Experience with integrated verification flows for processors with C and SV language is a plus • Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago etc. We’re doing work that matters. Help us solve what others can’t.