Lead Engineer - System on Chip (SoC) Verification

Job description

Lead Engineer - SOC Verification Position Overview: We are looking for a highly experienced Senior/Lead Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions. As a Senior Engineer in SoC Design Verification, you will play a key role in leading the SV/UVM based Subsystem and SoC verification strategy, planning, and execution for complex SoC projects. You will collaborate closely with cross-functional teams to ensure the highest quality and performance standards for our SoC products. This role requires deep technical expertise, leadership skills, and a passion for solving challenging verification problems. Key Responsibilities : Architect and develop reusable testbenches and Verification IP (VIP) using SystemVerilog and UVM to create scalable verification environments from scratch. Drive coverage closure , ensuring thorough functional coverage and code coverage across all SoC components. Implement and manage SV assertions and coverage-driven verification strategies to validate designs effectively. Utilize formal verification methods and tools to verify complex blocks and subsystems, complementing simulation-based verification. Develop comprehensive test plans and ensure their execution at the block, subsystem, and full-chip levels. Lead debug activities and identify design and verification bottlenecks early in the development cycle. Mentor junior engineers on best practices for SV/UVM, reusable verification, assertions, and coverage analysis. Collaborate with design, architecture, and system-level teams to define and implement verification strategies that meet stringent quality and performance goals. Drive continuous improvement of verification methodologies and tools to enhance team efficiency and quality. Requirements : 7+ years of experience in ASIC/SoC verification, specializing in SystemVerilog (SV) and Universal Verification Methodology (UVM) . Proven expertise in building reusable verification environments and VIP development from the ground up. Strong experience with coverage-driven verification , including functional and code coverage analysis and closure. Expertise in writing and debugging SV assertions and applying formal verification techniques. Hands-on experience with the full verification lifecycle, from test plan creation to regression analysis and closure. Strong problem-solving, debugging, and analytical skills in a fast-paced environment. Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field. Nice to Have : Experience with Pre-Silicon Validation , including test environment setup and validation strategies. Proficiency in FPGA prototyping and hardware emulation to complement verification strategies. Familiarity with ARM-based SoC architectures and high-performance SoC designs for applications such as IP Cameras, automotive, or AI/ML. Knowledge of low-power verification and formal verification techniques .