Memory Layout

Job description

**Brief About Tech Mahindra – Silicon Engineering** Tech Mahindra **Silicon Engineering** is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and industrial clients. The practice focuses on **VLSI, embedded systems, and platform engineering** , supporting customers from architecture and design through verification, validation, and sustenance engineering. The Silicon Engineering unit works across **IP, Subsystem, and SoC-level development** , offering capabilities in areas such as **Design Verification, RTL Design, DFT, Physical Design, Memory Design, Custom Layout, Post-Silicon Validation, Embedded Software, and System Modeling & Simulation** . Teams leverage industry-standard methodologies, tools, and design frameworks to deliver high-quality, production-ready silicon solutions. Backed by **Tech Mahindra's global engineering DNA** , the Silicon Engineering practice collaborates with leading semiconductor and technology clients worldwide, operating as an extended engineering arm to accelerate innovation, reduce time-to-market, and ensure reliable, scalable silicon platforms. It is part of Tech Mahindra's broader engineering-led growth strategy serving multiple global industries. **About the Role** We are looking for an experienced **Memory Layout Engineer** to join our advanced silicon design team. In this role, you will be responsible for the physical layout development of high-density memory IPs including **SRAM, Register Files, ROM, Compiler Memories, and Custom Memory Arrays** across advanced technology nodes. The ideal candidate should possess strong hands-on expertise in memory layout implementation and verification for **TSMC 2nm, 3nm, 5nm technologies or Samsung advanced nodes including 3nm, 4nm, and below** . You will collaborate closely with Circuit Design, Memory Design, Process, Verification, and Foundry teams to deliver highly optimized memory layouts meeting stringent power, performance, area, manufacturability, and reliability requirements. **Key Responsibilities** - Develop and implement full-custom layouts for **SRAM, Register Files, ROM, Memory Compilers, and Memory Macros** . - Design highly optimized layouts meeting **Power, Performance, Area (PPA), Yield, and Reliability** requirements. - Perform custom layout design for memory bit-cells, peripheral circuits, sense amplifiers, decoders, and control logic. - Execute layout implementation for advanced process nodes including: - **TSMC 2nm, 3nm, 5nm or Samsung 3nm, 4nm and advanced FinFET/GAA technologies** - Ensure layout compliance with foundry design rules, matching requirements, and reliability guidelines. - Perform layout verification using: DRC, LVS, ERC, PEX, Antenna Checks - Optimize layouts for area reduction, matching, parasitics, and manufacturability. - Work closely with circuit designers to resolve performance and layout challenges. - Analyze extraction results and support post-layout simulations. - Drive physical verification closure and tape-out readiness. - Collaborate with process technology and foundry teams to implement node-specific best practices. - Develop automation scripts and methodologies to improve layout productivity. - Participate in technical reviews, design audits, and customer discussions. **Qualification** **BE/BTech/ME/MTech** degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or related disciplines. **Required Skills** - Strong experience in **Memory Layout.** - Hands-on experience with: SRAM Layout, Register File Layout, Memory Compiler Layout, ROM Layout, High-Density Memory Arrays - Expertise in **TSMC 5nm, 3nm, 2nm** technologies or with experience with **Samsung 4nm, 3nm and advanced process nodes** . - Strong knowledge of: FinFET Technologies, Gate-All-Around (GAA) Technology, Multi-Patterning Requirements, Advanced Design Rules - Proficiency in layout tools such as: Cadence Virtuoso, Cadence Layout XL, Synopsys Custom Compiler - Experience with physical verification tools: Calibre DRC, Calibre LVS, Calibre PEX - Understanding of electromigration (EM), IR drop, reliability, and yield optimization. - Strong understanding of semiconductor manufacturing processes. - Experience in parasitic extraction and post-layout analysis. - Proficiency in scripting languages such as **SKILL, Tcl, Perl, Python, or Shell** . - Excellent debugging and problem-solving skills. **Preferred Skills** - Experience with advanced-node memory products for AI, HPC, Mobile, Automotive, and Networking applications. - Knowledge of SRAM bit-cell architecture and characterization. - Experience in technology migration across multiple foundries. - Exposure to custom analog layout concepts and matching techniques. - Experience with low-power memory design methodologies. - Familiarity with foundry signoff requirements and tapeout processes. - Experience supporting silicon bring-up and failure analysis activities. - Understanding of reliability checks including: ESD, Latch-up, EMIR Analysis, Aging Effects **Technology Node Experience (Mandatory)** **TSMC Nodes** - N5 / N5P (5nm) - N3 / N3E (3nm) - N2 (2nm) **Samsung Nodes** - SF4 (4nm) - SF3 (3nm GAA) - Advanced FinFET & GAA Technologies **Experience Range: 4-8 Years** **Why Join Tech Mahindra Silicon Engineering?** Join a world-class semiconductor engineering team working on next-generation memory technologies for leading global semiconductor companies. This role provides an opportunity to contribute to cutting-edge **SRAM and advanced memory IP development on TSMC 2nm/3nm/5nm and Samsung 3nm/4nm technologies** , enabling the future of AI, HPC, Mobile, Automotive, and Data Center platforms.