Principal Engineer-Physical Design

Job description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Summary: We are seeking an experienced Senior Principal Engineer / Senior Manager – Physical Design Lead to lead the implementation and delivery of next-generation, high-performance SoC products built on advanced process technologies. This role will be responsible for driving the complete physical design execution of large-scale SoCs, from floorplanning through tape-out, while achieving aggressive performance, power, area, and schedule targets.  The ideal candidate will have a proven track record delivering complex 3nm and/or 5nm SoCs, with deep expertise in physical implementation of extremely high-speed designs incorporating large digital subsystems, high-speed SerDes interfaces, mixed-signal blocks, and advanced power management architectures.  Key Responsibilities: • Lead the end-to-end physical design execution of large and complex SoCs from floorplanning through GDS signoff.  • Own implementation strategy, execution planning, risk management, and tape-out readiness.  • Drive floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, signal integrity, IR/EM closure, and physical verification.  • Collaborate closely with architecture, RTL, verification, DFT, package, analog, and product engineering teams to optimize implementation quality and schedule.  • Define chip-level implementation methodologies and best practices to achieve challenging frequency, power, and area goals.  • Lead timing closure for complex multi-clock, high-frequency designs.  • Partner with package and system teams to optimize overall product performance and signal integrity.  • Drive implementation of advanced low-power architectures and ensure successful power-performance-area (PPA) optimization.  • Lead physical design reviews, signoff reviews, and tape-out milestones.  • Mentor senior physical design engineers and establish implementation excellence across the organization.  • Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.  • 15-20+ years of experience in ASIC/SoC physical design.  • Proven experience leading physical design teams for large-scale, high-performance SoCs.  • Demonstrated success delivering advanced-node products, preferably at 3nm and/or 5nm technology nodes.  • Extensive experience across:  Floor planning and Partitioning, Power Planning, Placement and Optimization, Clock Tree Synthesis (CTS), Routing and Congestion Analysis, Timing Closure, Signal Integrity Analysis, IR Drop and Electromigration (EM) Closure, Physical Verification and Signoff. • Deep understanding of advanced-node implementation challenges including variation management, power integrity, and manufacturability.  • Strong knowledge of industry-standard physical design and signoff flows.  • Proven ability to lead large cross-functional teams and manage complex execution schedules. Preferred Qualifications • Experience implementing:   • High-performance SoCs operating at aggressive frequency targets  • Large-scale switching and interconnect architectures  • Network-on-Chip (NoC) based designs  • High-bandwidth data movement fabrics  • Multi-billion transistor designs  • Experience integrating and closing timing on:   • High-speed SerDes subsystems  • Mixed-signal and analog IPs  • Advanced PHY technologies  • Memory controller and high-speed interface designs  • Strong understanding of package-level and system-level impacts on physical implementation and timing closure.  • Experience with advanced packaging and multi-die/chiplet architectures.  • Exposure to AI, HPC, networking, data-center, connectivity, or memory infrastructure products.  • Prior experience with high-performance switch fabrics, Ethernet switching, UALink, or similar interconnect technologies is desirable.  • Advanced Low-Power Expertise (Must Have)  • The successful candidate must have hands-on experience architecting and implementing advanced power optimization techniques in advanced-node SoCs, including:  • Multi-voltage and multi-power domain designs  • Dynamic Voltage and Frequency Scaling (DVFS)  • Power gating and retention strategies  • Clock gating methodologies