Principal Engineer - Verification / AMS / SerDes

Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Central Engineering AMS‑IP delivers high‑quality analog and mixed‑signal IP and verification for Marvell’s advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high‑speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first‑time‑right silicon, reduced integration risk, and faster time‑to‑market through strong design‑verification convergence and system‑level validation. What You Can Expect Role Summary The Principal Engineer will provide technical and methodological leadership across complex high‑speed SerDes, AMS, and Central Engineering verification programs. This role requires deep hands‑on expertise combined with the ability to define verification strategy, influence architecture, mentor senior engineers, and drive execution excellence across multiple projects and nodes. Key Responsibilities • Own end‑to‑end verification strategy and execution for complex SerDes / AMS / mixed‑signal IPs across multiple process nodes (e.g., 5nm, 3nm, 2nm). • Define and drive verification architecture spanning digital, AMS, firmware‑assisted, and system‑level verification. • Lead design‑verification convergence, influencing architecture, register definition, calibration flows, and feature feasibility. • Drive resolution of complex cross‑domain issues involving RTL, AMS, firmware, VIPs, and silicon behaviors. • Serve as the technical authority and escalation point for hard verification, coverage, debug, and sign‑off challenges. • Lead Gate‑Level Simulation (GLS) strategy, power‑aware verification, CDC/RDC validation, and post‑silicon correlation. • Define verification approaches for new features. • Mentor juniors, raising the bar on technical rigor, ownership, and execution discipline. • Drive methodology, tooling, and productivity improvements, including automation and AI‑assisted verification where applicable. • Proactively identify technical and schedule risks and drive early mitigation across teams. What We're Looking For Required Technical Qualifications • 14+ years of strong hands‑on experience in verification of IP / AMS systems. • Deep expertise in one or more areas:     • High‑speed SerDes (PCIe, Ethernet, D2D, PAM4/PAM2)     • AMS / Mixed‑Signal verification     • Register modeling, firmware‑driven flows • Strong proficiency in SystemVerilog, UVM, and advanced verification methodologies. • Experience with protocol/VIP integration (Synopsys, Cadence, Mentor, Avery, etc.). • Hands‑on experience with GLS, power‑aware verification, timing‑aware flows, and silicon bring‑up support. • Ability to analyze and debug issues spanning pre‑silicon to post‑silicon correlation. • Strong understanding of system‑level behavior, not just block‑level verification. Leadership & Behavioral Expectations • Acts as a technical multiplier, enabling success across multiple teams and projects. • Leads through influence, credibility, and ownership, not hierarchy. • Makes sound trade‑offs under ambiguity, balancing quality, schedule, and risk. • Communicates complex technical issues with clarity and structure to diverse audiences. • Models engineering excellence, integrity, and accountability. • Invests in developing others, scaling impact beyond personal execution. Nice‑to‑Have / Differentiators • Experience defining verification frameworks reused across IPs / programs. • Innovation in AI‑ass