Senior Design Verification Engineer (DFx)

Job description

We are actively looking for experienced DFX DV Engineers to join our team in Bangalore and contribute to advanced SoC/ASIC development programs. 📍 Location: Bangalore 💼 Experience: 8 – 15 Years 🔧 Key Responsibilities: • Develop and execute comprehensive verification plans using SystemVerilog and UVM • Perform functional verification of SoC/IP components with a strong focus on DFX features • Build, maintain, and enhance UVM-based testbenches and environments • Debug failures across simulation, emulation, and silicon stages • Collaborate closely with Design and DFT teams to ensure testability and coverage closure • Analyze and validate test patterns (ATPG/ATE) for manufacturing readiness • Drive coverage closure and ensure high-quality verification sign-off • Support post-silicon validation and bring-up activities 📡 Required Skills: • Strong hands-on experience in SystemVerilog and UVM • Solid understanding of SoC/IP verification methodologies • Experience with DFX/DFT concepts such as scan, ATPG, and testability • Good debugging and analytical problem-solving skills • Exposure to multi-level verification (IP, subsystem, and SoC level) • Ability to work independently while collaborating effectively in a team environment 🌟 What We’re Looking For: • Self-driven engineers with a strong sense of ownership • Individuals who can handle complex verification challenges and deliver quality results • Team players who thrive in a fast-paced, collaborative environment