Senior Lead Engineer – Memory design

Job description

Summary: We are seeking a Lead Memory Design Engineer to join NXP’s NVM IP design group in Bangalore, India. This role involves leading and managing a diverse NVM IP portfolio, developing and maintaining automated IP management solutions, and collaborating with third-party NVM IP vendors and NXP product design teams to deliver high-quality, scalable NVM IP solutions across multiple business verticals. Job Qualification: • BS or MS in Electronics or Electrical Engineering with +7 years of experience in either Analog design or Memory design (SRAM/NVM) or Foundation IP design (IO/standard cells). • Hands-on experience in scripting and flow automation • Experience collaborating with and leading cross-functional, multi-disciplinary teams across the full lifecycle—from requirements definition through GDS implementation • Hands-on experience or sound knowledge of quality managed design flows, tools and methodologies (Cadence and Synopsys) • Knowledge of NVM technology, macro architecture and design would be a significant advantage • Excellent communication skills with proven experience in multi-site team collaboration Job responsibilities: As the Senior NVM IP Lead Engineer for our newly formed Bangalore team, you will be part of a Global NVM design department.  You will be leading the NVM IP benchmarking, onboarding, release and support competence for a wide 3rd-party NVM and NXP-proprietary IP platform including Logic-NVM, Flash, RRAM and MRAM. Your responsibilities will encompass: • NVM IP benchmarking for a given product and technology requirements • Execute IP onboarding (IP design kit preparation and verification) and release to product team • Support product design teams with NVM IP integration and troubleshooting • Develop and maintain an automated IP onboarding and release flow to ensure flawless and efficient execution • Maintain 3rd-party NVM and NXP-proprietary NVM IP portfolio spanning across the whole technology spectrum of the company from 180nm to 5nm • Interact directly with 3rd-party vendors and silicon foundries • Team up with NXP NVM design team in Bangalore, EU and US • Manage and drive the complete NVM IP development lifecycle, ensuring quality and timely execution • Drive proactive cross-functional coordination with digital design, reliability, and test engineering leads to enable on-time delivery of NVM IP • Track and monitor NVM IP development, ensuring timely and clear reporting to key stakeholders • Maintain strong stakeholder relationships to ensure alignment and smooth execution of deliverables. • Mentor junior engineers growing in the NVM field More information about NXP in India... #LI-7013