Senior Staff Design Verification

Job description

**Staff Engineer (Design Verification)Key Responsibilities:** - Lead and execute verification plans for various blocks within the SOC , with expertise in one or more domains CPU, DDR, Multimedia, Interconnects, Security, Peripherals, Power - Develop and enhance testbenches and verification environments using advanced automation techniques. - Collaborate closely with design and architecture teams to identify and resolve specification gaps and ensure comprehensive verification coverage. - Lead the SOC level verification activities from Specification phase to tape out - Expertise in DV closure using C, SV, UVM tests - Mentor and guide junior verification engineers, providing technical leadership and support. - Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. - Continuously improve verification processes and methodologies to enhance efficiency and effectiveness. - Good problem solving , analytical and debugging skill is must. **Qualifications:** - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - 12+ years of experience in SOC verification - Proficiency in verification languages and methodologies, including C , System Verilog, UVM, and scripting languages (Python, Perl, etc.). - Strong understanding of microarchitecture and SOC integration. - Experience with simulation, emulation, and formal verification tools. - Excellent problem-solving skills and attention to detail. - Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment. **Preferred Qualifications:** - Experience with low-power design verification and performance verification. - Familiarity with machine learning and AI-based verification approaches.