Senior Staff Engineer - Power Integrity

Job description

**Job Description** Senior Staff Engineer - Power Integrity / IR drop analysis Roles & Responsibilities: - The PI Signoff / IR Drop Analysis Lead is responsible for Signoff level IR drop, Power/Signal EM analysis of a Subsystem and Full SoC - He is responsible for running EM and Static/Dynamic IR analysis for various modes/power scenarios, root cause failures, provide fixing solutions - Responsible for EM and IR drop analysis (vector and vectorless) for both block and full chip designs for various power modes and scenarios. - Provide feedback / improvement / fixing suggestions to various stake holders like owners for Power, package, pattern, physical design, timing, etc - Analyze weakness area(s) in the design and provide fixing solutions. - Automation for reporting, debug, fixing suggestions/ECOs. - Setting up and Maintaining the environment for the overall PI analysis - Provide training to junior folks in the team to enhance their productivity and to extract quality work. **Main Requirements and Qualifications** - 12+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysis - Hands-on experience on RedHawk-SC or Voltus, preferably both - Hands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designs - Experience in leading block level or chip level IR/EM analysis - Ability to debug and resolve issues with inputs like – design data, library info, package, bump locations/RDL routing - Automation skills in TCL/Perl/awk/Python/Unix shell - Team player who is able to autonomously plan and perform tasks - Experience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the job - Worked on technologies 16nm and below, preferably on N7 and lower nodes - Exposure on designing power mesh especially on low power, power shut off designs - Some exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime)