Sr Staff Mask Design Engineer

Job description

**Company Description** Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. **Business Unit Description** The **Power Product Group (PWR)** is responsible for delivering power management solutions across automotive, computing, consumer, and industrial markets. Within PWR, the **Automotive System Power (ASP) division** focuses on **automotive power management and system power solutions** , supporting advanced vehicle architectures and safety‑critical applications. ASP brings together expertise in **automotive system power, system attach PMICs, and automotive battery management ICs** , delivering highly reliable solutions that meet stringent automotive quality, functional safety, and long‑term reliability requirements. The division works closely with cross‑functional teams across **design, layout, technology, test, and manufacturing** to deliver **robust SoC and IP solutions** for automotive customers worldwide. As part of the global PWR organization, ASP operates in a **multisite, multicultural environment** , emphasizing strong collaboration, technical excellence, and alignment across product lines to support Renesas’ automotive growth strategy. **Job Description** We are looking for an **experienced Sr Staff Mask Design Engineer** to join a highly skilled layout organization working on **Analog and Mixed‑Signal ICs for Automotive applications** . The role involves defining, developing, and delivering **high‑quality, manufacturable IC layouts** using industry‑standard technologies and tools. The successful candidate will contribute at **block and top level** , support or lead layout activities, collaborate closely with design and cross‑functional teams, and ensure robust physical implementation that meets performance, reliability, and quality requirements. **Job Purpose** The purpose of this role is to **deliver robust, high‑quality physical layouts** for complex analog and mixed‑signal ICs, ensuring manufacturability, reliability, and on‑time delivery, while contributing to layout methodology, team capability, and continuous improvement. **Key Responsibilities** As a Sr Staff Mask Design Engineer, you will be responsible for: - Implementing physical layouts for Automotive Business Line products at IP, block, and/or SoC level - Driving and delivering floorplanning activities for blocks and top‑level designs - Participating in power supply strategy definition and signal distribution between blocks - Delivering analog and mixed‑signal layout blocks and contributing to top‑level floorplan strategy - Applying state‑of‑the‑art layout techniques for device matching, parasitic reduction, ESD protection, latch‑up prevention, and yield optimization - Executing and signing off physical verification flows, including DRC, LVS, ERC, DFM, and parasitic extraction (PEX) - Working according to Analog‑on‑Top and Mixed‑Signal‑on‑Top layout methodologies - Attending relevant project and design reviews, reporting progress, risks, and schedule impacts - Collaborating closely with design, verification, CAD, and technology teams to minimize rework and resolve physical implementation issues - Identifying root causes and proposing solutions for issues observed during first silicon or prototype evaluation - Contributing to design‑for‑quality, ensuring layouts are verified, validated, and suitable for long‑term reliability and zero‑defect goals - Supporting or leading layout team activities, including task planning, execution, and knowledge sharing - Participating in and contributing to training activities, technical documentation, and layout guidelines - Taking a proactive role in personal development, continuous learning, and methodology improvement **Qualifications** **Education & Experience** - Bachelor’s or Master’s degree in Electrical, Electronics, or Microelectronics Engineering - 8+ years of experience in Analog and Mixed‑Signal IC layout design - Proven experience delivering complex layouts at IP, block, and/or SoC level - Experience in automotive or safety‑critical semiconductor products is highly desirable **Technical Skills** - Strong expertise in analog layout techniques, including: - Floorplanning and top‑level integration - Device matching and symmetry - Parasitic management - Latch‑up prevention and ESD protection - Solid understanding of electronics, semiconductor physics, and fabrication processes - Hands‑on expertise with layout and verification tools, including: - Cadence Virtuoso / Virtuoso XL (OA, PVS) - Mentor Graphics Calibre (DRC, LVS, PEX, DFM) - R3D and related parasitic extraction tools - Experience with advanced CMOS BCD technologies - Experience using Mixed‑Signal‑on‑Top (MSoT) flows - Ability to define and execute advanced floorplan strategies **Soft Skills & Ways Of Working** - Strong tea