Tapeout Engineer

Job description

**About the team** This position is on TI’s Advanced Technology Development (ATD) Mask Technology and Pattern Generation (MTPG) team. We support mask building, reticle generation, scribe array generation, layout generation & verification methodologies. **Tapeout Engineer** Seeking motivated Tapeout engineer - Supporting product and test chip PG’s across various technologies at TI **Job description:** - Conversion of product or technology development test chip layouts (LAFF, GDS) into fracture data - Preparing mask orders for shipment to vendors and managing the integrity and archival of data that is generated through this process. (Mask Data Preparation) - generate reticle floorplan databases - Drive automations for use in the PG/Tapeout process. - Collaborate with & guide various teams within Advanced Technology Development (process development, PDK), EDA and business units to ensure the necessary information is available to complete the PG process. - Ensure consistent application of methodologies and best practices **Required Key Skills** - Understanding of Layout and basics of fabrication process (FEOL/BEOL) - Knowledge of Mask data tools like Cadence Virtuoso, (Pegasus designrev / Mentor calibredrv - Maintain a high standard for cycle time and quality **Educational Qualifications** Bachelors / Master’s degree in Computer Science, Electrical/Electronic Engineering or related field with (2-5) years of Hardware Engineering or related work experience.