Technical Writer – Hardware Interface Compliance & Certification

Job description

Job Requirements At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Position Overview We are looking for a Technical Writer specializing in Hardware Compliance and Certification to document, structure, and drive the formal certification deliverables for our silicon and platform interfaces. In this role, you will work at the intersection of Hardware Engineering, Silicon Validation, and external standards bodies (such as the MIPI Alliance) to produce clear, audit-ready compliance documentation. You will be responsible for translating complex electrical, timing, and protocol validation data for I2C, SPI, QSPI, and MIPI (C-PHY/D-PHY, CSI/DSI) into rigorous Compliance Test Plans, Conformance Statements, Certification Filing Packages, Application Notes, and Hardware Errata. Key Responsibilities • Certification & Compliance Documentation:• Author, curate, and maintain formal compliance test reports, Implementation Conformance Statements (ICS), and Test Assertion Sheets for I2C, SPI, QSPI, and MIPI (C-PHY, D-PHY, CSI-2, DSI-2) interfaces. • Prepare and package end-to-end technical documentation required for formal certification submissions, interoperability workshops (e.g., MIPI Plugfests), and third-party audit labs. • Maintain up-to-date compliance matrixes mapping internal validation test results directly to official standards specifications (MIPI Alliance specs, NXP I2C specifications, JEDEC/vendor QSPI norms). • Engineering Collaboration & Data Synthesis:• Partner closely with Silicon Validation, Signal Integrity (SI), PHY Design, and Embedded Firmware engineers to extract raw test data, oscilloscope captures, and protocol traces. • Synthesize raw test outputs into structured, clear documentation (including pass/fail criteria, electrical margins, setup/hold limits, eye-diagram analyses, and timing diagrams). • Document protocol edge cases, hardware errata, and register-level workarounds for customer integration manuals and Silicon Errata sheets. • Developer & Customer Enablement Collateral:• Draft technical application notes, hardware integration guidelines, and pinout/routing compliance checklists for customer reference designs. • Create precise, high-quality timing diagrams, state machine charts, and interface connection schematics using tools like Visio, Draw.io, or WaveDrom. • Process & Document Lifecycle Management:• Own the document review and release lifecycle via Product Lifecycle Management (PLM) systems, ensuring all certification records meet traceability and version-control requirements. • Track active specification changes within standards bodies (e.g., updates to MIPI CSI/DSI specs) and proactively identify required revisions in internal documentation. Qualifications & Requirements Education & Experience • Bachelor’s degree in Technical Communication, Electrical Engineering, Computer Engineering, or a related technical discipline. • 3–6+ years of technical writing experience within the semiconductor, consumer electronics, or embedded hardware industries, with a focus on hardware compliance, silicon validation, or interface specifications. Domain & Technical Knowledge • Interface Literacy: Strong conceptual and functional understanding of serial and high-speed I/O interfaces:• I2C & SPI/QSPI: Bus topology, clock stretching, rise/fall times, multi-IO modes (Single/Dual/Quad/Octal SPI), timing constraints. • MIPI Standards: Familiarity with PHY architectures (D-PHY, C-PHY) and upper-layer protocols (CSI-2, DSI-2), including High-Speed (HS) vs. Low-Power (LP) transitions and lane configuration guidelines. • Interpretation of Hardware Data: Ability to read and accurately interpret:• Scope captures (eye diagrams, jitter metrics, rise/fall profiles). • Timing diagrams, bus state machines, and register bitfield maps. • Official industry conformance documents and test suites. • Tooling Mastery:• Standard authoring platforms: Markdown, AsciiDoc, DITA/XML, MadCap Flare, FrameMaker, or Confluence. • Version control systems: Git, Perforce, or SVN. • Timing/diagramming tools: WaveDrom, timing diagram editors, Visio, or Illustrator. Preferred Qualifications • Prior experience writing formal certification filings or conformance test plans for standards consortiums (MIPI Alliance, USB-IF, PCI-SIG, or VESA). • Basic understanding of automated test logs (e.g., Python test runner logs, SCPI/VISA test report outputs).