UCIe/D2D Post Si Validation Engineer

Job description

**Job ID** 2026-17756 **Date posted** Jul. 23, 2026 **Location** Bengaluru, India **Category** Hardware Engineering **Job Description: D2D/UCIe Functional Validation Engineer** **Role Overview** We are looking for a **Die-to-Die (D2D)/UCIe Functional Validation Engineer** with **3 to 8 years of experience** in silicon validation, high-speed interface validation, firmware-based validation, and system-level debug. The candidate will be responsible for validating **UCIe-based die-to-die interfaces operating at various UCIe 1.1 Spec defined data rates** on complex multi-die and chiplet-based SoC platforms. The role involves validation of the UCIe PHY, Adapter, protocol stack, sideband interface, link initialization, training, reliability mechanisms, power-management flows, and end-to-end data transfer between dies. The engineer will develop and execute validation plans, create test cases, support pre-silicon and post-silicon bring-up, debug complex link failures, and collaborate with architecture, design, PHY, firmware, packaging, signal integrity, and platform teams. The ideal candidate should have a strong understanding of high-speed serial or parallel interfaces, UCIe architecture, die-to-die communication, PHY training, firmware-controlled link initialization, and silicon debug methodologies. **Key Responsibilities** - Perform functional validation of UCIe-based D2D interfaces on pre-silicon and post-silicon platforms. - Validate UCIe links operating at **8, 16, 24, 32 GT/s etc., per lane** across supported link widths and package configurations. - Develop, enhance, and maintain validation test plans and test cases for the UCIe PHY, Adapter, protocol layer, sideband interface, and end-to-end data paths. - Support silicon and platform bring-up, including reset sequencing, clock initialization, PHY initialization, link training, parameter exchange, transition to mission mode, and traffic enablement. - Validate UCIe link initialization and training across all supported speeds, widths, lane configurations, voltage conditions, temperature conditions, and process corners. - Verify speed negotiation, link-width negotiation, lane mapping, lane reversal, lane disablement, lane repair, spare-lane usage, and link retraining mechanisms. - Validate UCIe protocol mappings such as PCIe, CXL, streaming, and raw-mode traffic, where applicable to the platform. - Validate interfaces between the UCIe Adapter and protocol or logic layers, including RDI, FDI, or equivalent implementation-specific interfaces. - Develop and execute end-to-end traffic tests between chiplets using register accesses, memory transactions, DMA traffic, streaming traffic, cache-coherent traffic, and platform-specific protocols. - Validate bidirectional and simultaneous traffic across multiple D2D links and chiplets. - Verify protocol reliability mechanisms, including CRC checking, retry, replay, error detection, error reporting, link recovery, and data integrity. - Validate sideband communication, initialization messages, management transactions, reset handshakes, error notifications, and power-management messages. - Validate link state transitions, including initialization, active operation, retraining, recovery, low-power entry and exit, reset, and link shutdown. - Validate warm reset, cold reset, link reset, die reset, firmware restart, surprise reset, and error-recovery scenarios. - Perform negative testing by injecting protocol, PHY, lane, CRC, timeout, malformed packet, retry, replay, and sideband errors. - Validate link behavior under lane failures, marginal lanes, degraded channel conditions, clock disturbances, voltage variations, and thermal stress. - Characterize link stability, BER, eye margins, timing margins, voltage margins, lane-to-lane skew, jitter tolerance, and long-duration reliability. - Execute stress scenarios involving maximum bandwidth, bidirectional traffic, multi-link concurrency, repeated retraining, reset loops, power-state transitions, and thermal or voltage stress. - Measure bandwidth, latency, protocol efficiency, utilization, retry overhead, and performance scaling across different speeds and link widths. - Develop and debug low-level firmware for UCIe initialization, PHY configuration, link training, register programming, error injection, traffic generation, and status monitoring. - Develop bare-metal tests and firmware-based validation sequences for early silicon bring-up. - Develop automation scripts for test execution, configuration sweeps, register dumps, log parsing, failure detection, and result analysis. - Debug silicon failures using firmware logs, PHY logs, protocol traces, register dumps, waveform captures, scan dumps, counters, and platform telemetry. - Use oscilloscopes, BERTs, logic analyzers, protocol analyzers, JTAG debuggers, and other lab equipment to analyze D2D link behavior. - Work closely with architecture, RTL design, verification, PHY, firmware, packaging, signal integrity, power, clocking, and platform teams to identify root causes and drive issues to closure. - Participate in reviews of UCIe architecture, PHY behavior, Adapter functionality, protocol flows, register definitions, firmware sequences, and validation coverage. - Create and maintain validation documentation, including test plans, test-case specifications, bring-up checklists, debug guides, issue reports, coverage reports, and execution summaries. - Track validation progress, report risks and blockers, and support defect triage through Jira, Bugzilla, or equivalent issue-management systems. Improve validation infrastructure, automation frameworks, regression environments, debug tools, and coverage methodology. - #LI-PS2 *Our* ***10x mindset*** *guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work:*https://careers.arm.com/en/10x-mindset ## **Accommodations at Arm** At Arm, we want to build extraordinary teams. If you need an adjustment or an a