Physical Design (PD) Lead

Job description

Physical Design with Synopsys Tool Exp: Key Responsibilities Physical Design Implementation • Own complete Physical Design flow from synthesis handoff to GDSII. • Perform Floor planning, Power Planning, Placement, CTS, Routing, Physical Optimization, and ECO implementation. • Drive block-level and full-chip design closure on advanced FinFET nodes. • Execute congestion analysis and optimization to achieve PPA targets. Timing Closure • Perform timing analysis using Synopsys PrimeTime. • Resolve setup, hold, transition, capacitance, and noise violations. • Drive MCMM timing closure across multiple corners and modes. • Implement timing ECOs and optimize critical timing paths. Physical Verification & Signoff • Run and debug DRC/LVS/ERC violations using industry-standard signoff tools. • Analyze and resolve physical design issues impacting manufacturability. • Ensure successful tapeout readiness. Power & Signal Integrity • Perform IR Drop and EM analysis. • Optimize power distribution networks. • Perform signal integrity checks and noise analysis to ensure robust silicon performance. Design Optimization • Drive area, power, and performance optimization. • Work closely with RTL, DFT, STA, and P&R teams to achieve design convergence. • Support Design-for-Manufacturability (DFM) requirements. Required Technical Skills Synopsys Tool Expertise • Strong expertise in: • Synopsys ICC2 • Fusion Compiler • PrimeTime • StarRC • IC Validator • Design Compiler (Good to Have) Physical Design Skills • Floorplanning • Power Planning • Placement Optimization • Clock Tree Synthesis (CTS) • Routing & Optimization • Timing Closure • ECO Closure • Signoff Closure • Low Power Implementation FinFET Experience • Mandatory hands-on experience in: • 16nm FinFET • 12nm FinFET • 7nm FinFET • 5nm FinFET (Preferred) Signoff Expertise • MCMM Timing Closure • Signal Integrity Analysis • Crosstalk Analysis • IR Drop Analysis • EM Analysis • DRC/LVS Closure Roles and Responsibilities A seasoned technical leader with deep expertise in semiconductor design and development, the Senior Principal Engineer plays a pivotal role in driving innovation across all phases of chip development — from architecture and RTL design to physical implementation, verification, and silicon validation. This role is responsible for setting technical direction on cutting-edge projects, influencing product roadmaps, and ensuring the successful delivery of high-performance, low-power, and cost-effective integrated circuits. Acting as a mentor and technical advisor, the Senior Principal Engineer collaborates with cross-functional teams across architecture, design, verification, DFT, and packaging to push the boundaries of silicon technology while aligning engineering execution with business and product strategies.