Senior Engineer & Technical Lead: Analog Layout

Job description

Position: Sr Engineer / Staff Engineer / Technical Lead Analog Layout (PMIC | Non-FinFET Technologies): Only Immediate Joiner Required Location: Bangalore / Hyderabad Experience: 3-10 Years Employment Type: Full-Time About Cyient Semiconductor Cyient Semiconductor is rapidly expanding its Analog Mixed Signal and Power Management Design teams and is looking for highly skilled Analog Layout professionals with strong experience in PMIC development and Non-FinFET process technologies. If you are passionate about building high-performance Power Management ICs and have delivered successful tape-outs on mature process nodes, this is an excellent opportunity to work with leading global semiconductor customers on cutting-edge products. Position Summary We are hiring Sr Engineers, Staff Engineers, and Technical Leads with strong expertise in Analog Layout Design for PMIC products across higher process nodes and BCD technologies. This role involves end-to-end ownership of custom analog layouts, close collaboration with design teams, and contribution to successful silicon execution. Key Responsibilities • Design and execute full custom analog layouts from floorplanning through tape-out. • Develop layout for PMIC building blocks including: • LDOs • Buck Converters • Boost Converters • Charge Pumps • Bandgap References • Comparators • Current Mirrors • Power Switches • Oscillators • Voltage References • Perform layout optimization for area, matching, performance, reliability, and manufacturability. • Implement advanced layout techniques: • Common Centroid • Interdigitation • Symmetry Matching • Shielding • Guard Rings • Latch-up Prevention • Run and resolve: • DRC • LVS • ERC • PERC • Antenna Checks • EM/IR Analysis • Collaborate with Analog Design, Verification, Reliability, and Foundry teams. • Support tape-out activities and silicon debug when required. • Lead layout reviews and mentor junior engineers (Staff Engineer / Technical Lead levels). Mandatory Skills Technical Expertise • 5+ years of experience in Analog Layout Design. • Strong experience in PMIC Layout Development. • Proven expertise in Non-FinFET / Mature Process Nodes: • 28nm • 40nm • 55nm • 65nm • 90nm • 110nm • 130nm • 180nm Layout Methodologies • Device Matching Techniques • Common Centroid Layout • Interdigitated Structures • Guard Ring Implementation • ESD Aware Layout • Latch-up Prevention • High Voltage Layout Considerations • Reliability and Yield Optimization EDA Tools • Cadence Virtuoso XL • Virtuoso Layout Suite • Calibre DRC/LVS/ERC/PERC • Parasitic Extraction Tools Preferred Skills • Experience in BCD Technologies. • Exposure to Automotive PMICs. • Experience with High Voltage (HV) and Low Voltage (LV) devices. • Knowledge of Foundry Technologies: • TSMC • TI BCD • GlobalFoundries • Tower Semiconductor • UMC Technical Lead / Staff Engineer Expectations • Lead complete block and top-level layout execution. • Drive project planning and layout closure. • Interface with customers and global stakeholders. • Mentor junior team members and conduct layout reviews. • Ensure adherence to design quality and tape-out schedules. Ideal Candidate Profile Strong PMIC layout background with multiple successful tape-outs. Expert in Non-FinFET analog layout methodologies. Hands-on experience with mature process nodes and BCD technologies. Ability to independently drive complex layout blocks from concept to silicon. Excellent problem-solving and stakeholder management skills. Interested candidates, kindly share updated CV to Rajanikant.Sharma@cyientsemi.com