Senior Lead Engineer

Job description

Job Requirements At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. What You Will Do • Develops and drives Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Actively works on power analysis, power optimization, simulation and roll-ups using Synopsys PTPX and RTLA. • Collaborating with the Various SoC and IP teams on various power projections and requirements, including silicon power capture and correlation with pre-si estimates. • Performed data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation. • Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction. What You Will Bring • Hands-on with Prime Power, PPRTL, PRRTL, PTPX for pre & post synthesis power estimation and analysis. • Experience to physical design flows (Fusion-Compiler/RTL-A) for quick power trials • Scripting in Python & TCL We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace. Work Experience • Develops and drives Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Actively works on power analysis, power optimization, simulation and roll-ups using Synopsys PTPX and RTLA. • Collaborating with the Various SoC and IP teams on various power projections and requirements, including silicon power capture and correlation with pre-si estimates. • Performed data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation. • Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction.