Standard Cells Lead

Job description

About Tata Electronics Private Limited Tata Electronics Pvt. Ltd. is a prominent global player in the electronics manufacturing industry, with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly & Test, Semiconductor Foundry, and Design Services. Established in 2020 as a greenfield venture of the Tata Group, the company aims to serve global customers through integrated offerings across a trusted electronics and semiconductor value chain. With a rapidly growing workforce, the company currently employs over 65,000 people and has significant operations in Gujarat, Assam, Tamil Nadu, and Karnataka, India. Tata Electronics is committed to creating a socioeconomic footprint by employing many women in its workforce and actively supporting local communities through initiatives in environment, education, healthcare, sports and livelihood. Job Title: Lead Standard Cells / Logic Cells Circuit Designer Job Summary We are seeking a seasoned and innovative Lead Standard Cells / Logic Cells Circuit Designer to spearhead the development of high-performance, low-power standard cell libraries for advanced semiconductor nodes. This role demands deep technical expertise, leadership capabilities, and a passion for pushing the boundaries of digital circuit design. Solid hands on working knowledge in Standard cells circuit design, with low power and high-performance flip-flops, latches, multibit flip flops, clocking cells, different power domain level-shifters, optimized for power and area. Key Responsibilities • Lead the design and optimization of standard cells and logic cells across multiple technology nodes. • Architect and implement transistor-level designs with a focus on PPA (Performance, Power, Area) trade-offs. • Collaborate with process technology, EDA, and physical design teams to ensure seamless integration and manufacturability. • Oversee cell characterization, modelling, and validation using industry-standard tools and methodologies. • Drive innovation in cell architecture, layout techniques, and automation flows. • Conduct design reviews, ensure quality assurance, and manage sign-off processes. • Mentor junior engineers and contribute to team skill development. • Interface with cross-functional teams to align cell library development with broader SoC and ASIC design goals. Required Qualifications • M.S. or Ph.D. in Electrical Engineering, Microelectronics, or related field. • 10+ years of experience in standard cell or logic cell design on older process nodes from 180nm to 22nm technology. • Strong foundation in CMOS device physics, digital circuit design, and layout optimization. • Proficiency in EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, Calibre, Liberate, SiliconSmart, etc. • Experience with scripting languages (Python, Perl, TCL, Shell, ICV) for design automation. • Excellent problem-solving, analytical, and communication skills. • Proven track record of technical leadership and project execution. Preferred Qualifications • Experience with FinFET and GAA (Gate-All-Around) transistor technologies. • Familiarity with reliability-aware design (aging, BTI, HCI, EM) and variation-aware design techniques. • Exposure to AI/ML-based optimization methods in circuit design and layout. • Knowledge of advanced characterization techniques including statistical timing and power modelling. • Experience in developing ultra-low power and high-speed cell architectures. • Contributions to open-source tools, IEEE publications, or industry standards. • Experience with cross-foundry PDKs and multi-node library development. • Understanding of EDA tool development or customization for cell design flows.